Common problems in PCB circuit design
1. Stacking of pads
1. The stacking of pads (except surface mount pads) means the stacking of holes. During the drilling process, the drill bit will be broken due to multiple drilling in one place, resulting in damage to the hole.
2. Two holes in the multilayer board are stacked. For example, one hole is an isolation plate and the other hole is a connection plate (flower pad), so that the film will appear as an isolation plate after drawing, and the formed one is invalid.
2. The abuse of graphics layer
1. Some useless connections were made on some graphics layers. It was originally a four-layer board, but more than five layers were planned, which caused a misunderstanding.
2. Save effort during planning. Take Protel software as an example to draw the lines on each layer with the Board layer, and use the Board layer to mark the line. In this way, when the light drawing data is performed, the Board layer is not selected, and the board layer is not selected. The connection is disconnected and the circuit is broken, or it may be short-circuited due to the selection of the marking line of the Board layer, so the graphic layer is kept intact and clear when planning.
3. Violation of conventional planning, such as component surface planning at the Bottom layer and welding surface planning at the Top, which is inconvenient for formation.
3. Random placement of characters
1. The SMD soldering pad of the character cover pad brings inconvenience to the continuity test of the printed circuit board and the soldering of the components.
2. If the characters are too small, it is difficult to form screen printing. If the characters are too large, the characters will be stacked on top of each other and it is difficult to distinguish them.
Four, single-sided pad aperture setting
1. Single-sided pads are generally not drilled. If the drilling needs to be marked, the aperture should be planned to be zero. If the value is planned, then when drilling data occurs, the coordinates of the hole appear in this direction, and there is a problem.
2. Single-sided pads such as drilling should be specially marked.
5. Draw pads with filler blocks
Drawing pads with filler blocks can be viewed through DRC when planning the circuit, but it is not good for processing. Therefore, similar pads cannot directly generate solder mask data. When solder resist is applied, the filler block area will be covered by the solder resist, resulting in It is difficult to solder the device.
pcba processing
6.
Because of the power supply of the patterned pad method, the ground layer is opposite to the image on the actual printed circuit board. All connections are isolated lines. The planner should be very clear about this. Here, by the way, care should be taken when drawing the isolation lines of several sets of power supplies or grounds, and no gaps should be left to short-circuit the two sets of power supplies, and the area of
Seven, the definition of the processing level is not clear
1. The single-sided board is planned on the TOP layer. If the front and back are not specified, the board may be equipped with components and the soldering may not be good.
2. For example, when planning a four-layer board, choose TOP mid1 and mid2 bottom four layers, but they are not placed in this order during processing, which requires explanation.
8. There are too many filler blocks in the planning or the filler blocks are filled with very thin lines
1. The gerber data is lost, and the gerber data is incomplete.
2. Because the filling blocks are drawn one by one with lines when processing the light drawing data, the amount of light drawing data that occurs is appropriately large, which increases the difficulty of data processing.
Nine, the surface mount device pad is too short
This is for the continuity test. For devices that are too densely mounted, the distance between the two pins should be appropriately small, and the pads should be appropriately thin. The test pins must be interleaved up and down (left and right), such as soldering. The disk plan is too short, although it does not affect the device installation, but it will make the test needle not staggered.
10. The distance of the large-area grid is too small
The margin between the same lines that make up a large area of
11. The distance between the large area copper foil and the outer frame is too close
The distance between the large area copper foil and the outer frame should be at least 0.2mm or more, because when the shape is milled, if it is milled onto the copper foil, it will simply cause the copper foil to warp and the solder resist drop caused by it.
12. The outline frame plan is not clear
Some customers have planned contour lines for Keep layer, Board layer, Top over layer, etc., and these contour lines do not overlap. It is difficult for PCB manufacturers to determine which contour line shall prevail.
13. Uneven graphics planning
When pattern plating is performed, the plating layer is uneven, which affects the quality.
14. Use grid lines when the copper area is too large to avoid blistering during SMT.