Checklist in PCB design

No.1 data input stage
Whether the information received in the process is complete (including: schematic diagram, *.brd file, bill of materials, PCB design specification, PCB design or change requirements, standardization requirements specification, process design specification and other documents).
Make sure the PCB template is up to date.
Whether the clock layout is reasonable.
Confirm that the positioning device position of the template is correct.
PCB design description, PCB design or change requirements and standardization are clear.
Make sure that the forbidden devices and wiring areas on the outline drawing are reflected on the PCB template.
Compare the outline drawings, and confirm that the dimensions and tolerances marked on PCB are correct, and the definition of metallized holes and nonmetallic holes is accurate.
After confirming the accuracy of PCB template, it is best to lock the structure file to avoid misoperation of the moved position.
No.2 Post-layout inspection stage
1. device inspection
Confirm whether all device packages are consistent with the unified library of the company, and whether the package library has been updated (check the running results with viewlog). If not, be sure to update Symbols.
Motherboard and daughter board, single board and back board have corresponding confirmation signals, corresponding positions, correct connector directions and silk screen marks, and daughter board has anti-misoperation measures, so daughter board should not interfere with devices on motherboard.
Whether the components are placed 100%.
Open the place-bound of the TOP and BOTTOM layers of the device to see if the DRC caused by overlap is allowed.
Whether Mark is enough and necessary.
Heavy components should be placed near the supporting points or edges of PCB to reduce the warpage of PCB.
Confirm whether all device packages are consistent with the unified library of the company, and whether the package library has been updated (check the running results with viewlog). If not, be sure to update Symbols.
Motherboard and daughter board, single board and back board have corresponding confirmation signals, corresponding positions, correct connector directions and silk screen marks, and daughter board has anti-misoperation measures, so daughter board should not interfere with devices on motherboard.
Whether the components are placed 100%.
Open the place-bound of the TOP and BOTTOM layers of the device to see if the DRC caused by overlap is allowed.
Whether Mark is enough and necessary.
Heavy components should be placed near the supporting points or edges of PCB to reduce the warpage of PCB.
It’s best to lock the devices related to the structure after they are laid out, so as to prevent misoperation from moving their positions.
Within 5mm around the crimp socket, there are no components whose height exceeds that of the crimp socket on the front, and no components or solder joints on the back.
Confirm whether the device layout meets the technological requirements (focusing on BGA, PLCC and SMD socket).
Metal shell components, pay special attention not to collide with other components, and leave enough space.
The related devices of the interface should be placed as close as possible to the interface, and the backplane bus driver should be placed as close as possible to the backplane connector.
Whether the CHIP device with wave soldering surface has been converted into wave soldering package.
Whether there are more than 50 manual solder joints.
Horizontal installation should be considered for axially inserting higher components on PCB. Leave room for sleeping. And consider the fixing method, such as the fixed pad of crystal oscillator.
For devices that need heat sinks, make sure that there is sufficient distance between them and other devices, and pay attention to the height of major devices within the range of heat sinks.
2. Functional inspection
Whether the digital circuit and analog circuit devices of the digital-analog board are separated in layout, and whether the signal flow is reasonable.
A/D converters are placed across analog-digital partitions.
Whether the clock layout is reasonable.
Whether the layout of high-speed signal devices is reasonable.
Whether the terminating device has been properly placed (source matching series resistance should be placed at the driving end of the signal; The matched series resistance is placed in the middle position; The matching series resistance of the terminal should be placed at the receiving end of the signal)
Taking the planes of signal lines with different levels as reference planes, whether the connecting capacitance between the reference planes is close to the signal routing area when crossing the plane division area.
Whether the layout of the protection circuit is reasonable and conducive to division. Whether the fuse of the single board power supply is placed near the connector, and there are no circuit elements in front of it.
Make sure that the circuits of strong signal and weak signal (power difference is 30dB) are laid separately.
Whether the number and position of decoupling capacitors of IC are reasonable.
Whether to place the devices that may affect EMC experiments according to the design guidelines or referring to successful experiences. For example, the reset circuit of the panel should be slightly close to the reset button.
3. Fever
Heat-sensitive components (including liquid dielectric capacitors and crystal oscillators) should be as far away from high-power components, radiators and other heat sources as possible.
Whether the layout meets the thermal design requirements, and the heat dissipation channel (according to the process design documents).
4. Power supply
Whether the IC power supply is too far away from the IC.
And whether the LDO’s surrounding circuit layout is reasonable.
Whether the circuit layout around the module such as power supply is reasonable.
Whether the overall layout of the power supply is reasonable.
5. Rule setting
Whether all simulation constraints have been correctly added to the Constraint Manager.
Whether the physical and electrical rules are set correctly (pay attention to the constraint settings of power network and ground network).
Is the spacing between Test Via and Test Pin set enough?
Whether the thickness and scheme of laminate meet the design and processing requirements.
Have all differential line impedances with characteristic impedance requirements been calculated and controlled by rules?
No.3 post-wiring inspection stage
1. Mathematical model
Whether the wiring of digital circuit and analog circuit has been separated, and whether the signal flow is reasonable.
If A/D, D/A and similar circuits are divided into ground, will the signal lines between the circuits go from the bridge point between the two places (except differential lines)?
Signal lines that must span the gap between divided power sources should refer to the complete ground plane.
If the formation design is divided into zones without division, it is necessary to ensure that digital signals and analog signals are wired in zones.
2. Clock and high-speed part
Whether the impedance layers of high-speed signal lines are consistent.
Whether the differential signal lines and similar signal lines are of equal length, symmetrical and parallel to each other.
Make sure the clock line is on the inner layer as far as possible.
Confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired according to the 3W principle as far as possible.
Whether there is no test point for bifurcation on clock, interrupt, reset signal, 100 MB/Gigabit Ethernet and high-speed signal.
Whether the distance between low-level signals such as LVDS and TTL/CMOS signals is 10H(H as far as possible (h is the height of the signal line from the reference plane).
Do the clock and high-speed signal lines avoid passing through dense via areas or wiring between device pins?
Whether the clock line has met the requirements (SI constraint) (whether the clock signal line has fewer holes, short line and continuous reference plane, and the main reference plane is GND； as far as possible; If the GND main reference plane layer is changed during layer changing, it is a GND via within 200mil from the via; If the main reference plane of different levels is changed during layer changing, is there a decoupling capacitor within 200mil of the via).
Whether differential pairs, high-speed signal lines and various buses have met the requirements of (SI constraint).
3. EMC and reliability
For crystal oscillator, whether a layer of ground is laid under it; Whether the signal line is prevented from crossing between the device pins; For high-speed sensitive devices, is it possible to avoid signal line crossing between device pins?
There can be no acute angle or right angle on the signal wiring of single board (generally, it turns continuously at an angle of 135 degrees, and it is best to use circular arc or chamfered copper foil after calculation for RF signal lines).
For double panels, check whether the high-speed signal line is wired next to its return ground wire; For multilayer boards, check whether the high-speed signal line is routed as close to the ground plane as possible.
For the adjacent two layers of signal routing, try to route vertically.
Avoid the signal line passing under the power supply module, common mode choke, transformer and filter.
Try to avoid long-distance parallel routing of high-speed signals on the same floor.
The edge of the board also has digital ground, analog ground, and protected ground, and whether there are shielded through holes at the dividing edge; Whether multiple ground planes are connected by holes; Whether the via distance is less than 1/20 of the wavelength of the highest frequency signal.
Whether the signal traces corresponding to surge suppression devices are short and thick on the surface layer.
Make sure that there are no isolated islands, excessive slots, long ground cracks caused by excessive through-hole isolation disks or dense through-holes, slender strips and narrow passages in the power supply and stratum.
Whether there are ground vias (at least two ground planes are required) where there are many signal lines crossing layers.
4. Power supply and ground
If the power/ground plane is divided, try to avoid high-speed signal crossing on the divided reference plane.
Make sure that the power supply and ground can carry enough current. Whether the number of vias meets the load-bearing requirements (estimation method: line width of 1A/mm when the outer copper layer is 1oz thick, line width of 0.5A/mm in the inner layer, and double short-line current).
Whether the power supply with special requirements meets the requirements of voltage drop.
To reduce the edge radiation effect of the plane, the principle of 20H should be met as far as possible between the power layer and the stratum (if conditions permit, the more the power layer is indented, the better).
If there is a division of ground, whether the divided ground does not constitute a loop.
Whether different power planes of adjacent layers avoid overlapping.
Whether the isolation of protection ground, -48V ground and GND is greater than 2mm.
Whether the ground of -48V is only the signal reflux of -48V, which is not connected to other ground; If you can’t, please explain the reasons in the remarks column.
Is there a 10~20mm protective ground near the connector panel, and the layers are connected by double rows of staggered holes?
Whether the distance between the power line and other signal lines meets the safety requirements.
5. No cloth area
There should be no traces, copper skins and vias that may cause short circuit under the metal shell devices and heat dissipation devices.
There should be no traces, copper skins and vias around the mounting screws or washers that may cause short circuit.
Whether there is any wiring in the reserved position in the design requirements.
The distance between the inner layer of nonmetallic hole and the circuit and copper foil should be greater than 0.5mm(20mil), the outer layer should be 0.3mm(12mil), and the distance between the inner layer and the circuit and copper foil in the shaft hole of single-board pulling wrench should be greater than 2mm(80mil).
It is recommended that the copper and wire be larger than 2mm and the minimum is 0.5mm to the edge of the board.
The inner copper layer is 1 ~ 2 mm from the plate edge, with a minimum of 0.5 mm
6 bonding pad outgoing line
For CHIP components (0805 and below packages) mounted on two pads, such as resistors and capacitors, the printed lines connected with the pads should be led out symmetrically from the center of the pads, and the printed lines connected with the pads must have the same width. For leads with line width less than 0.3mm(12mil), this provision can be ignored.
The pad connected with the wider printed line should preferably be transited by a narrow printed line (0805 and below package).
Lines should be led out from both ends of pads of SOIC, PLCC, QFP, SOT and other devices as far as possible.
7. Screen printing
Whether the device tag number is missing, and whether the position can correctly identify the device.
Whether the device number meets the requirements of company standards.
Confirm the correctness of the pin arrangement order, the first pin mark, the polarity mark of the device and the direction mark of the connector of the device.
Whether the plug-in board direction marks of the mother board and the daughter board correspond.
Whether the backplane correctly identifies the slot name, slot number, port name and sheath direction.
Confirm whether the silk screen required by the design is added correctly.
Make sure that the anti-static and RF board signs have been placed (RF board is used).
8. Coding/barcode
Confirm that PCB code is correct and conforms to company specifications.
Confirm that the PCB coding position and level of the single board are correct (it should be on the upper left side of the A side, screen printing layer).
Make sure that the PCB coding position and level of the backplane are correct (it should be at the top right of B, with the outer copper foil surface).
Make sure there is a bar code laser printing white silk screen marking area.
Make sure there are no wires and vias larger than 0.5mm under the bar code box.
Make sure that there are no components with a height of more than 25mm within 20mm outside the bar code white screen printing area.
9. via hole
On the reflow soldering surface, the via hole cannot be designed on the pad (the distance between the normally opened via hole and the pad should be greater than 0.5mm (20mil), and the distance between the green oil covered via hole and the pad should be greater than 0.1 mm (4mil). The method: open the Same Net DRC, check the DRC, and then close the Same Net DRC).
The arrangement of via holes should not be too dense, so as to avoid a large-scale fracture of power supply and ground plane.
The hole diameter of the drilled hole should be no less than 1/10 of the plate thickness.
10. process
Whether the device placement rate is 100% or not, and whether the routing rate is 100% (if it does not reach 100%, please specify in the remarks).
Whether the Dangling line has been adjusted to the minimum has been confirmed one by one for the reserved Dangling line.
Whether the process problems fed back by the process department have been carefully checked.
11. Large area copper foil
For large-area copper foils on Top and bottom, if there is no special need, use grid copper (oblique net for single board and orthogonal net for back board, with line width of 0.3mm (12 mil) and spacing of 0.5mm (20mil)).
Component pads in large copper foil area should be designed as flower pads to avoid virtual soldering; When there is a current requirement, first consider widening the ribs of the flower pad, and then consider full connection.
When copper is distributed in a large area, dead copper (isolated island) without network connection should be avoided as much as possible.
Large-area copper foil should also pay attention to whether there are illegal connections and unreported DRC.
12. Test points
Whether the test points of various power sources and grounds are sufficient (at least one test point per 2A current).
Confirm that all networks without test points can be streamlined after confirmation.
Verify that no test points are set on plug-ins that are not installed in production.
Test Via and Test Pin have been fixed (applicable to changing the test needle bed).
13、DRC
The Spacing Rule of Test via and Test pin should be set to the recommended distance, and DRC should be checked. If DRC still exists, DRC should be checked with the minimum distance setting.
Set the open constraint to the open state, update the DRC, and check whether there are any impermissible errors in the DRC.
Confirm that the DRC has been adjusted to the minimum, and confirm the DRC that cannot be eliminated one by one.
14. Optical positioning point
Make sure that the PCB surface with mounted components has optical positioning symbols.
Make sure that the optical positioning symbol is not pressed (silk screen printing and copper foil routing).
The background of the optical positioning point should be the same, and confirm that the center of the optical point used in the whole board is ≥5mm away from the edge.
Confirm that the coordinate values of the optical positioning reference symbols of the whole board have been assigned (it is recommended to place the optical positioning reference symbols in the form of devices), and they are integer values in millimeters.
For IC with pin pitch less than 0.5mm, and BGA device with center pitch less than 0.8 mm(31 mil), optical positioning points should be set near the diagonal of the components.
15. Welding resistance inspection
Make sure that all pads with special requirements are properly windowed (pay special attention to the design requirements of hardware).
Whether the via hole under BGA is processed to cover the oil plug hole.
Test whether vias other than vias have been opened with small windows or covered with oil plugs.
Whether the window opening of the optical positioning point avoids the exposure of copper and wires.
Whether the chips, crystal oscillators and other devices that need copper skin for heat dissipation or grounding shielding have copper skin and open windows correctly. Devices fixed by solder should have green oil to block the large-area diffusion of solder.
16. Borehole drawing
The PCB thickness, number of layers, color of screen printing, warpage and other technical specifications of Notes are correct.
Whether the layer name, stacking sequence, dielectric thickness and copper foil thickness of the laminated drawing are correct; Whether impedance control is required and whether the description is accurate; Whether the layer name of the overlay is consistent with its light drawing file name.
Turn off the Repeat code in the setting table, and the drilling accuracy should be set to 2-5.
Whether the table and drilling file are up to date (when the hole is changed, it must be regenerated).
Whether there is abnormal hole diameter in the table, and whether the diameter of the pressure fitting is correct; Whether the bore tolerance is marked correctly.
Are the through holes of the fortress listed separately and marked “filled vias”?
17. Light painting
As far as possible, RS274X format should be used for the output of light files, and the accuracy should be set to 5:5.
Whether art_aper.txt is up to date (274X is unnecessary).
Whether there is an abnormal report in the log file of the output photo file.
Edge and island confirmation of negative layer.
Use the photo-drawing checking tool to check whether the photo-drawing file is consistent with PCB (the board change should be compared with the comparison tool).
18. Complete set of documents
PCB file: product model _ specification _ single board code _ version number.brd.
Backplane liner design document: product model _ specification _ veneer code _ version number-CB [-t/b] .brd.
PCB processing file: PCB code. zip (including photo files, aperture tables, drilling files and ncdrill.log of each layer; The mosaic board also needs the mosaic file *.dxf provided by the process), and the backing board file: PCB code -CB[-T/B].zip (including drill.art, *.drl and ncdrill.log) is attached to the back board.
Process document: product model _ specification _ single board code _ version number-gy.doc.
SMT coordinate file: product model _ specification _ single board code _ version number -SMT.txt (when outputting coordinate file, confirm that Body center is selected, and only when the origin of all SMD device libraries is confirmed to be the device center can Symbol origin be selected).
PCB structure file: product model _ specification _ single board code _ version number -MCAD.zip (including. DXF and. EMN files provided by structural engineers).
Test file: product model _ specification _ single board code _ version number -TEST.ZIP (including testprep.log and coordinate file of untest.lst or *.drl test points).
Filing drawings: product model specification-single board name-version number.pdf (including: front cover, front page, silk screen printing of each layer, circuit of each layer, drilling drawing, and back plate with liner drawing).
9. Standardization
Make sure the information on the cover and front page is correct.
Confirm that the drawing serial number (corresponding to the sequential distribution of PCB layers) is correct.
Make sure the PCB code on the drawing frame is correct.