Design of Skycar Kinetis 60(K60) Clock System

Freescale Kinetis series is a microcontroller based on ARM CORTEX-M4 introduced by Freescale.
Design of Freescale K60 Clock System
As shown in the above figure, the Freescale K60 clock system can find that there are four source clock sources of the device: ① Internal reference clock sources, including Fast IRC and Slow IRC (IRC-Internal Reference Clock) ② External reference clock sources, with only one EXTAL pin as the clock input. The active crystal oscillator can be used to realize ③ external crystal resonator, and EXTAL and XTAL pins are used to input ④ external 32K RTC resonator. The clock input for real-time clock can be seen in the figure. To provide clock signal for the system, the key is to finally generate MCGOUTCLK output. MCGOUTCLK can provide Core/system clocks, Bus clock, FlexBus clock and Flash clock after frequency division. There are three ways to generate MCGOUTCLK: ① It is directly provided by the internal reference clock source Fast IRC, which is integrated in the chip (including Slow IRC) with a frequency of 2M ② It is provided by FLL or PLL module ③ It is directly provided by external clock, including external reference clock source (1 pin input), XTAL_CLK generated by external crystal resonator via internal OSC logic and clock output of RTC OSC logic. Generally, MCGOUTCLK is generated by PLL or FLL frequency doubling, and the official routine of Freescale is finally generated by PLL module. It can be seen in the figure that the clock input of PLL module is OSCCLK or RTC OSC logic. My board uses external reference clock source to provide PLL clock, and finally generates MCGOUTCLK by PLL frequency multiplication. That is, EXTAL–>PLL module –>MCGOUTCLK.
2. About the clock mode
As you can see from the figure, the chip contains 8 working clock modes, plus Stop mode. After the system is RESET, it directly enters the default FEI mode. In the figure, f-FLL, p-PLL, e-enable or EXTAL (external clock), b-bypass, I-internal (internal reference clock), L-low power.
FLL enabled, internal reference clock (FEI), the internal reference clock provides the clock of FLL, and FLL drives MCGOUT.
FLL enabled, external reference clock (FEE), the external reference clock provides the clock of FLL, and FLL drives MCGOUT.
FLL bypass, internal reference clock (FBI). Although FLL is in operation, it is driven by the internal clock reference source to drive MCGOUT. FLL bypass, external reference clock (FBE), although FLL is in operation, MCGOUT is driven by external clock reference source. PLL bypass, external reference clock (PBE), although the PLL is in operation, it is driven by the external clock reference source to drive MCGOUT • PLL enabled, external reference clock (PEE), which provides the clock of PLL, and PLL drives MCGOUT.
The blpifll and PLL are both disabled, and the internal clock reference drives MCGOUT.
Blpefll and PLL are both disabled, and the external clock reference drives MCGOUT.
Since the system enters FEI mode by default after restart, our goal is to jump to PEE mode, so it involves mode transformation. In the graph, FEI to PEE can’t jump directly, so it must be converted by other modes.