1. Xilinx ISE traditional FPGA design process
The basic process of developing FPGA by using Xilinx ISE software includes code input, function simulation, synthesis, simulation after synthesis, implementation, simulation and verification after wiring and debugging after work.
1) circuit design or code input
The design of FPGA can directly draw the schematic diagram, but in the case of complex systems, the schematic diagram of this method is quite complex, so it is gradually eliminated, and ISE retains this function.
Now the design input of FPGA is mainly Verilog and VHDL hardware languages. Verilog language has simple syntax and is widely used in Asia.
VHDL is recognized as the standard hardware description language by IEEE and U.S. Department of Defense, and it is common in Europe.
2) Functional simulation
After the basic FPGA module is written, it is necessary to use simulation tools to simulate the designed module to verify whether the basic function of the module meets the design. Function simulation is also called pre-simulation. Commonly used simulation tools are
Modelsim of Model Tech, VCS of Synopsys, NC-Verilog and NC-VHDL of Cadence. Function simulation can speed up the design of FPGA and reduce errors in the design process.
3) Synthesis
Synthesize is to translate design inputs such as hardware language or schematic diagram into logical connections (netlists) composed of basic logical units such as AND, OR, RAM, flip-flops, etc., and optimize the generated logical connections according to constraints, and output files such as edf and edn.
4) Implementation
Implementation can be understood as mapping the logic to the resources of the target device structure by using the implementation tools, determining the optimal layout of the logic, selecting the wiring channels for connecting the logic with the input and output functions, and generating corresponding files (such as configuration files and related reports). It can be divided into the following five steps.
(1) Conversion: Convert and merge multiple design files into one design library file.
(2) Mapping: mapping the logic gates in the netlist into physical elements, that is, the process of dividing the logic design into configurable logic blocks, input and output blocks and other resources in the programmable logic array.
(3) Layout and wiring: Layout refers to taking out the defined logic and input and output blocks from the map and assigning them to the physical positions inside the FPGA, usually based on some advanced algorithm, such as minimum division, simulated annealing and general stress direction relaxation, etc. Routing refers to the use of automatic routing software to try to complete all logical connections by using routing resources to select paths. Because the latest design and implementation tool is timing driven, that is, the timing analysis of the whole signal channel is performed during the layout of the device, the constraint conditions can be used to operate the wiring software to fulfill the performance requirements specified in the design. In the process of layout, the timing information can be extracted at the same time to form a report.
(4) Time sequence extraction: an anti-bid file is generated for subsequent time sequence simulation.
(5) Configuration: Generate the required bit stream file for FPGA configuration.
Options can be set during the implementation process. Because it supports incremental design, it can be wired repeatedly, and each wiring uses the last wiring information to make the wiring better or achieve the design goal. In the process of implementation, the download form of default configuration should be set to make the subsequent bit stream download normal.
5) Time series analysis
In the process of design and implementation, after mapping, it is necessary to analyze the timing of the delay of a designed actual functional block and the estimated wiring delay. After the layout, the static timing analysis of the functional block delay and the actual wiring delay of the actual layout should also be carried out. From a certain program, static timing analysis can be said to be the most important step in the whole FPGA design. It allows the designer to analyze all critical paths in detail and get an orderly report, and the report contains other debugging information, such as fan-out or capacitive load of each network node. Static timing analyzer can be used to check the logic and timing of the design, so as to calculate the performance of each channel, identify reliable traces, and detect the coordination of setup and hold times. Timing analyzer does not require users to generate input excitation or test vectors. Although Xilinx and altera have timing analysis tools on the FPGA development kit, when they have the third-party specialized timing analysis tools, they only use the third-party specialized timing analysis tools for layout and wiring. Generally, FPGA manufacturers have interfaces with the third-party timing analysis tools in their design environment. Primetime of Synopsys is a good time series analysis tool, which can achieve better results. Save the synthesized netlist file in db format, which can be opened in PrimeTIme environment. Using this software to check and analyze the time sequence of the critical path or the path that the designer is interested in, and ending the time sequence of the original design again can improve the working frequency or reduce the time of the critical path. Similar to the synthesis process, static timing analysis is also a repetitive process, which is closely linked with the layout and routing steps. This operation usually has to be performed many times until the timing constraints are well met.
In the process of synthesis and timing simulation, PrimeTIme is interactively used for timing analysis. After meeting the design requirements, the final physical verification of FPGA chip before chip placement can be carried out.
6) Debugging and loading configuration
The last step of the design is online debugging or writing the generated configuration file into the chip for testing. Use iMPACT in ISE.