Detailed parameters of Hi3516AV200 processor

HI3516AV200, as a new industry-specific SOC designed for high-definition IP cameras, integrates a new generation of ISPs, and uses the latest H.265 video compression encoder and the latest H.265 video compression encoder in the industry. Advanced low-power technology and architectural design. These features enable Hi3516AV200 to continue to maintain its leading position in terms of low bit rate, high image quality and low quality. Power consumption Hi3516AV200 adopts hardware to support 90 or 270 rotation and lens distortion correction, meeting the requirements of various surveillance application scenarios. It also supports S3A algorithm, allowing customers to design various IP camera models with integrated camera cores. Hi3516AV200 integrates POR, RTC and audio CODEC, and supports various sensors. And the EBOM cost of the high-definition IP camera based on Hi3516AV200 is greatly reduced. Hi3516AV200HisilSDK has high stability and ease of use, supports rapid mass production, and facilitates the system layout of DVR, NVR and IP cameras. ProcessorCore 800MHzA7core,supporting32KBI-cache,32KBD-cache,and128KBL2cache 1.25GHzA17core,supporting32KBI-cache,32KBD-cache,and256KBL2cache Neonacceleration,integratedFPU ARM@big-LITTLEarchitecture VideoEncoding H.264BP/MP/HP H.265MainProfile I/P/Bframe,dual-P-framereference MJPEG/JPEGbaselineencoding IntelligentVideoAnalysis IVE, which supports various intelligent analysis applications, such as motion detection, perimeter defense and video diagnosis. VideoandGraphicsProcessing 3D denoising, image enhancement and dynamic contrast improvement Anti-flicker of output video and graphics 1/30x to 16x video scaling Seamlessly splicing 2-channel video 1/2x to 2x graphics scaling OSD superposition of the first eight areas is coded The video is superimposed into two layers (video layer and graphics layer). ISP 2 channel independent ISP processing Adjustable 3A functions (AE, AWB and AF) FPN removal Highlight compensation, backlight compensation, gamma correction and color enhancement. Defect pixel correction, denoising and digital image stabilization antifog Lens distortion correction and fisheye correction Rotate the picture by 90 or 270. Image mirroring and flipping The sensor has built-in WDR, 4F/3F/2F frame/line-based WDR, and local tone mapping. The second channel handled by isp only supports built-in wdr, 2f frames/line-based wdr and local tones. Map, draw a map of, plan ISP tuning tool based on PC AudioEncoding/Decoding Speech coding/decoding using software complying with multiple protocols Comply with G.711, G.726 and ADPCM protocols. 3A audio function (AEC, ANR and ALC) SecurityEngine AES, DES and 3DES encryption and decryption algorithms implemented by hardware RSA1024/2048/4096 signature verification algorithm implemented by hardware Hash -SHA1/256 and HMAC_SHA1/256 tamper-proof algorithms implemented by hardware Integrated 512-bit OTP storage space and hardware random number generator AudioInterfaces Integrated audio codec supporting 16-bit audio input and output I2S interface for connecting to external audio codec Dual-channel differential MIC input for reducing background noise. PeripheralInterfaces POR External reset input Internal RTC Integrated three-channel SARADC Five UART interfaces Ir interface, I2C interface, SSP main interface and GPIO interface. 8 PWM interfaces (4 independent interfaces and 4 interfaces multiplexed with other pins) Two SD3.0/SDIO3.0 interfaces supporting SDXC One USB3.0/USB2.0 A PCIe2.0 interface in master/slave mode