HI3519V101 processor HD input processor

A7@800MHz，32KBI-Cache，32KBD-Cache/128KBL2cache
A17@1.25GHz，32KBI-Cache，32KBD-Cache/256KBL2cache
HI3519V101 supports Neon acceleration and integrates FPU processing unit.
ARM®big.LITTLE core architecture is supported.
video coding
H.264BP/MP/HP
H.265MainProfile
H.264/H.265 supports I/P/B frame and double P frame reference.
HI3519V101 supports MJPEG/JPEGBaseline encoding
HI3519V101 Video Coding Processing Performance
H.264/H.265 coding can support the maximum resolution of 16M(4608×3456)Pixel.
H.264/H.265 multi-stream real-time coding capability;
340 * 2160 @ 30fps+1080p @ 30fps+3840 * 2160 @ 2fps Snap
Support the maximum JPEG capture performance of 3840*2160@30fps
It supports five rate control modes: CBR/VBR/FIXQP/AVBR/QPMAP
Output code rate supports up to 100Mbps.
Support eight regions of interest (ROI) coding
Intelligent video analysis
Integrated intelligent analysis acceleration engine supports intelligent motion detection, perimeter defense, video diagnosis and other intelligent analysis applications.
And video graphics processing
Support 3D denoising, image enhancement and dynamic contrast enhancement.
Support anti-flicker processing of video and graphic output.
Support video 1/30 ~ 16x zoom function
Support seamless splicing of two videos.
Support graphics 1/2 ~ 2x scaling function
Pre-coding OSD superposition of 8 regions
Two layers (video layer, graphics layer) video graphics overlay
ISP
Support two independent ISP processes
3A(AE/AWB/AF) function is supported, and the control of 3A can be adjusted by the user.
Support to fixed pattern noise (FPN) function
Support strong light suppression, backlight compensation, Gamma and color enhancement.
Support bad point correction, denoising and digital image stabilization.
Support defogging
Support lens distortion correction and fisheye correction.
Support image rotation of 90 /270 degrees
Image Mirror and Flip are supported
SensorBuild-InWDR, 4F/3F/2F-Framebase/LinebaseWDR and LocalTonemapping are supported, and the second ISP only supports SensorBuild-InWDR, 2F-Framebase/LinebaseWDR and LocalTonemapping.
PC-side ISPtuningtools are provided.
Audio codec
The multi-protocol speech codec protocol supports G.711, G.726 and ADPCM through software.
Audio 3A(AEC/ANR/ALC) processing is supported.
HI3519V101 video interface
input
Two sensor inputs are supported, of which the maximum resolution of the main channel is 16M(4608×3456) and that of the second channel is 8M(4096×2160).
It supports 8/10/12/14BitRGBBayerDC timing video input, and the clock frequency is up to 150MHz.
Support video input interfaces of BT.601, BT.656 and BT.1120
The main channel supports up to 12xlanemipi/LVDS/sub-LVDS/hispi interface.
The second Sensor interface supports 4xLaneMIPI/LVDS/Sub-
LVDS/HiSPi interface
It supports docking with mainstream high-definition CMOSSensor such as SONY, Aptina, OmniVision and Panasonic.
Compatible with electrical characteristics of multiple Sensor parallel/differential interfaces
Provide programmable Sensor clock output
output
1 channel PAL/NTSC output and automatic load detection are supported.
Provide one BT.1120/BT.656 video output interface for external HDMI or SDI interface, and support 1080P@60fps output at maximum.
Support LCD output
audio interface
Audiocodec is integrated to support 16bit voice input and output.
I2S interface is supported, and docking with external Audiocodec is supported.
Support two-channel Mic differential input to reduce noise floor.
Peripheral interface
SupPORt por
Support external reset input
Support internal RTC
Integrated 3-channel LSADC
5 UART interfaces
IR interface, I2C interface, SSP main interface, GPIO interface
8 PWM interfaces (4 independent, 4 multiplexed with other pins)
Two SD3.0/SDIO3.0 interfaces, supporting SDXC
1 USB3.0/2.0Host/Device interface
1 PCIe2.0 master/slave mode
Support RGMII and RMII modes; 10/100Mbps full-duplex or half-duplex mode and 1000Mbps full-duplex mode are supported; TSO network acceleration is supported