Parameter characteristic structure of hi3520DV400 chip

This document introduces the characteristics and logic structure of hi3520DV400 chip, describes the functions, working modes and related register definitions of each module in detail, gives the interface timing relationship and related parameters in the form of charts, and describes the pin definitions and uses of the chip, its performance parameters and package size in detail.
Hi3520DV400 is a professional SOC chip developed for multi-channel high-definition (1080p/720p) and multi-channel clear (D1/960H)DVR products. Hi3520DV400 has built-in armA7 dual-core processor and high-performance H.265/H.264 video codec engine. It integrates a high-performance video/image processing engine with a number of complex image processing algorithms, provides HDMI/VGA high-definition display output capability, and also integrates rich peripheral interfaces. This SOC chip provides a low-cost analog HD /SDI solution with high performance and excellent image quality for customer products, and at the same time can greatly reduce the eBOM cost of related products.
Features:
Hi3520DV400 processor core
ARMCortexA7 dual-core @Max.1.3GHz
32KBL1I-Cache，32KBL1D-Cache
256KBL2Cache
Support NEON/FPU
Multi-protocol video codec
H.265Mainprofile,Level4.1 coding
H.265MainProfile,Level4.1 decoding
H.264 baseline/main/highprofilelevel 4.2 coding
H.264 baseline/main/highprofilelevel 4.2 decoding
MPEG-4SP,L0~L3/ASPL0~L5 Decoding
MJPEG/JPEGBaseline codec
Intelligent video analysis
Integrated intelligent analysis acceleration engine supports intelligent motion detection, perimeter defense, video diagnosis and other intelligent analysis applications.
And video graphics processing
Support pre-and post-processing such as de-interlace, sharpening, 3D denoising, dynamic contrast enhancement and mosaic processing.
Support anti-flicker processing of video and graphic output.
Support video 1/15 ~ 16x scaling
Support 1/2 ~ 2x scaling of graphics
Support 4 occlusion areas
Support OSD superposition of 8 areas
Audio codec
Hardware multi-protocol audio coding is implemented, and ADPCM, G.711 and G.726 are supported.
Software implementation of multi-protocol audio codec
Safety engine
Implement hardware AES/DES/3DES encryption and decryption algorithm
audio interface
3 unidirectional I2S/PCM interfaces
2 inputs, supporting 16 compound inputs.
1 output, supporting two-channel output
Support 16bit voice input and output