PCB Layout Design Skills of Non-isolated Switching Power Supply

A good PCB layout design can optimize the efficiency, slow down the thermal stress, and minimize the noise and interaction between traces and components. All this comes from the designer’s understanding of the current conduction path and signal flow in the power supply.
When a prototype power panel is powered on for the first time, the best situation is that it can not only work, but also be quiet and low in heat generation. However, this situation is rare.
A common problem of power supply is “unstable” switching waveform. Sometimes, the waveform jitter is in the sound band, and the magnetic elements will produce audio noise. If the problem lies in the layout of the printed circuit board, it may be difficult to find out the reason. Therefore, the correct PCB layout in the initial stage of switching power supply design is very critical.
The power supply designer should have a good understanding of the technical details and the functional requirements of the final product. Therefore, from the beginning of the PCB design project, the power supply designer should cooperate closely with the PCB layout designer on the key power supply layout.
A good layout design can optimize the power efficiency and reduce the thermal stress. More importantly, it minimizes noise and the interaction between traces and components. To achieve these goals, the designer must know the current conduction path and signal flow inside the switching power supply. To realize the correct layout design of non-isolated switching power supply, the following design elements must be kept in mind.
PCB layout planning
For the embedded dc/dc power supply on a large circuit board, in order to obtain the best voltage regulation, load transient response and system efficiency, it is necessary to make the power output close to the load device, and minimize the interconnection impedance and conduction voltage drop on the PCB traces. Ensure good air flow and limit thermal stress; If forced air cooling measures can be adopted, the power supply should be close to the fan position.
In addition, large passive components (such as inductors and electrolytic capacitors) must not block air flow through low surface-mounted semiconductor components, such as power MOSFET or PWM controllers. To prevent switching noise from interfering with analog signals in the system, it is necessary to avoid laying sensitive signal lines under the power supply as much as possible. Otherwise, it is necessary to place an internal grounding layer between the power layer and the small signal layer as a shield.
The key is to plan the position of power supply and the demand for circuit board space in the early design and planning stage of the system. Sometimes designers ignore this advice and focus on the more “important” or “exciting” circuits on large system boards. Power management is regarded as an after-the-fact work, and it’s not good for efficient and reliable power design to put the power on the extra space on the circuit board.
For multilayer boards, a good method is to lay DC ground or DC input/output voltage layer between the high-current power element layer and the sensitive small-signal wiring layer. Or the DC voltage layer of the formation provides an AC ground for shielding small signal traces from the interference of high-noise power traces and power elements.
As a general rule, the ground layer or DC voltage layer of multilayer PCB should not be separated. If this separation is inevitable, the number and length of traces on these layers should be reduced as much as possible, and the traces should be laid in the same direction as the heavy current to minimize the impact.
Power level layout
The switching power supply circuit can be divided into two parts: power level circuit and small signal control circuit. The power stage circuit contains components for transmitting large current. Generally, these components should be laid out first, and then small signal control circuits should be laid out at some specific points in the layout.
High-current traces should be short and wide to minimize the inductance, resistance and voltage drop of PCB. This is especially important for those traces with high di/dt pulse current.
The high-frequency decoupling capacitor CHF should be a ceramic capacitor with 0.1μF~10μF, X5R or X7R dielectric, which has extremely low ESL (effective series inductance) and ESR (equivalent series resistance). A larger capacitor dielectric (such as Y5V) may make the capacitance value drop greatly at different voltages and temperatures, so it is not the best material for CHF.
If there is no heat sink for surface mounting power MOSFET and inductor in PCB design, the copper foil area must have sufficient heat dissipation area. For DC voltage nodes (such as input/output voltage and power supply ground), it is reasonable to make the copper foil area as large as possible.
Multiple vias help to further reduce thermal stress. To determine the suitable copper foil area of high dv/dt switching node, it is necessary to make a design balance between minimizing dv/dt related noise and providing good heat dissipation capacity of MOSFET.
Power pad form
Pay attention to the pad forms of power components, such as low ESR capacitors, MOSFET, diodes and inductors.
For decoupling capacitors, the positive and negative vias should be as close to each other as possible to reduce the ESL of PCB. This is especially effective for low ESL capacitance. Capacitors with small capacitance and low ESR are usually expensive, and incorrect pad form and bad wiring will reduce their performance, thus increasing the overall cost. Generally, a reasonable pad form can reduce PCB noise, thermal resistance, trace impedance and voltage drop of high-current components to the greatest extent.
There is a common mistake in the layout of high-current power components, that is, the incorrect use of thermal relief. The use of hot air pads in unnecessary cases will increase the interconnection impedance between power components, resulting in greater power loss, and reduce the decoupling effect of small ESR capacitors. If holes are used in layout to conduct large current, make sure they are in sufficient quantity to reduce impedance. In addition, do not use hot air pads for these vias.
Control circuit layout
Keep the control circuit away from the high-noise switch copper foil area. For step-down converter, the good way is to place the control circuit near the VOUT+ terminal, while for step-up converter, the control circuit should be close to the VIN+ terminal, so that the power trace can carry continuous current.
If space permits, there should be a small distance (0.5-1 inch) between the control IC and the power MOSFET and inductor (which are all high-noise and high-heat components). If the space is tight and the controller is forced to be placed close to the power MOSFET and inductor, special attention should be paid to isolating the control circuit from the power components by ground or grounding traces.
The control circuit should have an independent signal (analog) ground different from the power level ground. If there are independent SGND (signal ground) and PGND (power ground) pins on the controller IC, they should be wired separately. For the control IC integrated with MOSFET driver, SGND should be used for IC pin of small signal part.
Only one connection point is needed between signal ground and power ground. The reasonable method is to return the signal to a clean point in the power formation. Only connecting two kinds of grounding traces under the controller IC can realize two kinds of grounding.
The decoupling capacitors of the control IC should be close to their respective pins. To minimize the connection impedance, it is a good way to connect the decoupling capacitor directly to the pin instead of via.
Loop area and crosstalk
Two or more adjacent conductors can generate capacitive coupling. A high dv/dt on one conductor will couple out current on another conductor through parasitic capacitance. In order to reduce the coupling noise of the power level to the control circuit, the high-noise switch wiring should be far away from the sensitive small-signal wiring. If possible, it is necessary to lay the high-noise wiring in different layers from the sensitive wiring, and use the internal stratum as a noise shield.
If space permits, the control IC should have a small distance (0.5-1 inch) from the power MOSFET and the inductor, which is noisy and hot.
The FET drivers TG, BG, SW and BOOST pins on LTC3855 controller have high dv/dt switching voltages. The LTC3855 pins connected to the most sensitive small signal nodes are: Sense+/Sense-, FB, ITH and SGND. If the sensitive signal traces are laid out close to the high dv /dt nodes, the grounding wire or ground layer must be inserted between the signal traces and the high dv/dt traces to shield the noise.
When laying out the gate drive signal, using short and wide traces helps to minimize the impedance in the gate drive path.
If a PGND layer is laid under the BG trace, the AC ground return current of the low FET will be automatically coupled into a path close to the BG trace. AC current will flow to the smallest loop/impedance it finds. At this time, the low gate driver does not need a separate PGND return trace. The best way is to minimize the number of layers through which the gate drive traces pass, so as to prevent the gate noise from spreading to other layers.
Among all small-signal traces, current detection traces are the most sensitive to noise. The amplitude of the detection signal is usually less than 100mV, which is equivalent to the amplitude of noise. Taking LTC3855 as an example, Sense+/Sense- traces should be laid in parallel with minimum spacing (Kelvin detection) to minimize the chance of picking up di/dt related noise.
In addition, the filter resistance and capacitance of current detection traces should be as close to IC pins as possible. This structure has the best filtering effect when noise is injected into a long detection line. If the inductor DCR current detection method with R/C network is adopted, the DCR detection resistor R should be close to the inductor, while the DCR detection capacitor C should be close to the IC.
If a via is used on the return path from the trace to Sense-, the via should not touch other internal VOUT+ layers. Otherwise, the via may conduct a large VOUT+ current, and the resulting voltage drop may destroy the current detection signal. Avoid laying current detection traces near high-noise switching nodes (TG, BG, SW and BOOST traces). For example, it is possible to place a ground layer between the current detection wiring layer and the power level wiring layer.
If the controller IC has differential voltage remote detection pins, it should adopt independent wiring for the positive and negative remote detection lines, and also adopt Kelvin detection connection.
Selection of route width
For a specific controller pin, the current level and noise sensitivity are unique, so it is necessary to select a specific trace width for different signals. In general, the small signal network can be narrower, using 10-15 mil wide traces; The large current network (gate drive, VCC and PGND) should adopt short and wide traces. The wiring of these networks is recommended to be at least 20mil wide.