Signal Integrity (SI) of high-speed PCB board design is abbreviated as SI.
Definition: The quality of the signal on the signal line is the ability of the signal to respond with the correct timing and voltage in the circuit.
High switching speed of integrated circuit chips (IC) or logic devices, incorrect layout of terminal elements or wrong wiring of high-speed signals will all cause signal integrity problems such as reflection, crosstalk, overshoot, undershoot, ringing, etc., which may cause the system to output incorrect data and the circuit to work abnormally or even completely.
Signal integrity and design of PCB
In the design of PCB, PCB designers need to integrate the layout and wiring of components, and what kind of SI problem solving methods should be adopted in each case, so as to better solve the signal integrity problem of PCB. In some cases, the choice of IC can determine the number and severity of SI problems. Switching time or edge rate refers to the rate of IC state transition. The faster the edge rate of IC, the higher the possibility of SI problems. It’s very important to properly terminate the devices in the ground. The common way to reduce the signal integrity problem in PCB design is to add terminating components on the transmission line. In the process of termination, the requirements of the number of components, signal switching speed and circuit power consumption should be weighed. For example, adding terminating components means that PCB designers can use less space for wiring, and it will be more difficult to add terminating components in the later stage of layout, because it is necessary to leave corresponding space for new components and wiring. Therefore, it should be clear whether to place terminating components at the early stage of PCB layout.
1. General principles for signal integrity design of high-speed pcb design:
How to define the number of PCB layers?
How many layers are used? How to arrange the contents of each layer most reasonably? For example, there should be several layers of signal layer, power layer and stratum, and how the signal layer and stratum are arranged alternately.
How to design a variety of power supply block systems?
Such as 3.3V, 2.5V, 3V, 1.8V, 5V, 12V, etc. The reasonable division of power layer and common ground is a very important factor for the stability of PCB.
How to configure decoupling capacitor?
Using decoupling capacitor to eliminate noise is a common method, but how to determine its capacitance? Where is the capacitor placed? What type of capacitor is used, etc?
How to eliminate ground bomb noise?
How does ground bomb noise affect and interfere with useful signals?
How to eliminate the Return Path noise? In many cases, the unreasonable circuit design is the key to the circuit failure, and the circuit design is often the most helpless work of engineers.
How to design the distribution of current reasonably?
Especially, it is very difficult to design the current distribution in electricity/stratum, and if the total current distribution in PCB is uneven, it will directly and obviously affect the unstable work of PCB.
There are some other common problems related to signal distortion, such as overshoot, undershoot, ringing, transmission line delay, impedance matching, crosstalk, glitch, etc., but these problems are inseparable from the above problems, and they are causal.
2. PCB design criteria to ensure signal integrity
The earlier the signal integrity (SI) problem is solved, the higher the design efficiency will be, thus avoiding adding terminal components after the circuit board design is completed. With the increase of IC output switching speed, almost all designs have encountered signal integrity problems regardless of the signal cycle. Even though SI problems have not been encountered in the past, with the increase of circuit operating frequency, There will be problems with signal integrity. SI and EMC experts have to conduct simulation and calculation before wiring PCB, and then, PCB design can follow a series of very strict design rules. Where in doubt, you can increase the number of terminating components, so as to obtain as much SI safety margin as possible. Power integrity (PI) is closely related to signal integrity (SI), The integrity of the power supply directly affects the signal integrity of the final PCB board. In many cases, the main reason for the signal distortion is the power supply system. At present, EMC design mainly adopts the design rules check method. It is very important that enterprises must gradually establish and improve the design specifications for products in specific fields of enterprises, and form a complete set of EMC design rules. These are very popular in large foreign companies, such as Samsung and SONY. These rules are checked by people or EDA software.
3. Electrostatic discharge (ESD) design of 3.PCB board
Many product design engineers usually start to consider the problem of electrostatic discharge (ESD) when the product enters the production process. If the electronic equipment can’t pass the ESD test, usually the final scheme will adopt expensive components, and it will be manually assembled in the manufacturing process, or even need to be redesigned. Therefore, the progress of the product is bound to be affected. Even experienced design engineers may not know which parts of the design are beneficial to ESD. Most electronic devices spend 99% of their life in an environment full of ESD, which may not come from the human body, furniture or even the device itself. It is rare for electronic equipment to be completely damaged by ESD. However, ESD interference is very common, which will lead to equipment locking, resetting, data loss and unreliability. The result may be that the electronic equipment often fails in the cold and dry winter, but it shows normal during maintenance, which is bound to affect users’ confidence in electronic equipment and its manufacturers.
4. The mechanism of 4.ESD
When one conductor that allows electricity approaches another conductor, a strong electric field will be established between the two conductors, resulting in breakdown caused by the electric field. When the voltage between two conductors exceeds the breakdown voltage of air and insulating medium between them, ESD arc will occur. Within 0.7ns to 10ns, the ESD arc current will reach tens of amps or even exceed 100A. The ESD arc will generate a strong magnetic field with a frequency range of 1MHz~500MHz, which will be inductively coupled to each adjacent wiring loop, and will generate a current of more than 15A and a high voltage of more than 4KV within 10cm from the ESD arc. The ESD arc will be maintained until the contact between two conductors is short-circuited or the current is too low to maintain the arc.
5. ESD resistant PCB layout and wiring design
Use multilayer PCB board structure as much as possible, and arrange special power supply and ground plane in the inner layer of PCB board. Bypass and decoupling capacitors are used. Try to make every signal layer close to a power layer or a ground layer. For high-density PCB with components on the top and bottom surfaces, short connecting lines and lots of padding, you can consider using inner wiring.
Ensure that the layout of each functional circuit and components between functional circuits is as compact as possible. For circuits or sensitive components that are susceptible to ESD, they should be placed near the center of PCB board, so that other circuits can provide some shielding effect for them. In areas that can be directly hit by ESD, a ground wire should be laid near each signal line.
At the I/0 interface of the equipment where ESD is easy to enter, and at the places where human hands often need to touch or operate, such as reset key, communication port, on/off key, function key, etc. Usually, a transient protector, a series resistor or a magnetic bead are placed at the receiving end.
Make sure that the signal line is as short as possible. When the length of the signal line is longer than 12 inches (30cm), a ground wire must be laid in parallel.
Ensure that the loop area between the signal line and the corresponding loop is as small as possible. For long signals, change the position of the signal line and the ground line every few centimeters or inches to reduce the loop area.
Ensure that the loop area between the power supply and the ground is as small as possible, and place a high-frequency capacitor near each power supply pin of the integrated circuit chip (IC).
If possible, the unused area should be filled with land, and the filling areas of all layers should be connected at intervals of < 2inch(5cm). Or when the length of the opening on the ground plane of the power supply exceeds 8mm, narrow wires should be used to connect the two sides of the opening. The reset line, interrupt signal line, or edge trigger signal line cannot be arranged near the edge of PCB. The annular ground vias are arranged around the whole periphery of the PCB board, so that the annular ground width of all layers is larger than 100mil as much as possible. Connect all layers annularly with holes every 500mil, and the distance between signal lines and annularly is > 20 mils (0.5 mm).