In a grounded desktop product, when the ESD contact discharge test with a test voltage of 6KV was conducted at the grounding terminal, the system was reset. In the test, try to disconnect the grounding terminal from the Y capacitor connected to the internal digital working ground, but the test result has not improved significantly.
Cause analysis
ESD interference enters the internal circuit of the product in various forms. For the tested product in this case, the test point is the grounding point, and most of the ESD interference energy will flow away from the grounding line, that is to say, the ESD current does not directly flow into the internal circuit of the product. However, the grounding line of this desktop device in the ESD test environment specified in IEC61000-4-2 standard is about 1m long, and the grounding line will generate a large grounding lead inductance (which can be estimated by 1uH/m). When the electrostatic discharge interference occurs (that is, when the switch K in Figure 1 is closed), the high frequency (rising edge less than 1ns) electrostatic discharge current cannot make the voltage at the grounding point of the tested product zero (that is, the voltage at point G in Figure 1 is not zero when K is closed). The non-zero voltage on that ground terminal will further enter the internal circuit of the product. Figure 1 has given the schematic diagram of ESD interference entering the PCB inside the product.
Figure 1 Schematic diagram of 1ESD interference entering the internal PCB of the product
It can also be seen from Figure 1 that CP1: (parasitic capacitance between discharge point and GND), CP2: (parasitic capacitance between PCB and reference grounding plate), working ground (GND) of PCB board and ESD gun (including ESD gun grounding wire) form an interference path, and the interference current is ICM.In this interference path, the PCB board is in it, obviously PCB is interfered by electrostatic discharge at this time.If there are other cables in the product, the interference will be more serious.
How does the interference cause the reset of the tested product? After careful inspection of the PCB of the tested product, it is found that the reset control line of the CPU in the PCB board is arranged at the edge of the PCB board and is outside the GND plane, as shown in Figure 2.
Then explain why the printed wiring arranged at the edge of the PCB is easy to be interfered with. It should start with the parasitic capacitance between the printed wire in the PCB and the reference grounding plate.There is a parasitic capacitance between the printed wire and the reference grounding plate. This parasitic capacitance will cause interference to the printed signal line in the PCB, and the common mode interference voltage will interfere with the printed line in the PCB. The schematic diagram is shown in Fig. 3.
It can be seen from Figure 3 that when the common mode interference (CMI voltage relative to the reference grounding plate) enters GND, an interference voltage will be generated between the printed line and GND in the PCB. This interference voltage is not only related to the impedance between the printed line and the GND of the PCB (z in Fig. 3), but also related to the parasitic capacitance between the printed line and the reference grounding plate.
Assuming that the impedance Z between the printed circuit and the GND of the PCB is constant, the larger the parasitic capacitance between the printed line and the reference grounding plate is, the greater the interference voltage Vi between the printed circuit and the GND of the PCB board, which is superimposed with the normal working voltage in the PCB, will directly affect the working circuit in the PCB.
Figure 2 actual PCB wiring diagram of tested product
Fig. 3 Schematic diagram of common mode interference voltage interfering with printing line in PCB
According to Formula 1 for calculating the parasitic capacitance between the printed wire and the reference grounding plate, the parasitic capacitance between the printed wire and the reference grounding plate depends on the distance between the printed wire and the reference grounding plate (i.e. h in Formula 1) and the equivalent effective area of the electric field formed between the printed line and the reference grounding plate (i.e. s in Formula 1).
Cp≈0.1xS/H（1）
CP: parasitic capacitance [pf] S: Equivalent area of printed wire [cm2] H: Height [cm] When the printed wire is arranged at the edge of PCB, a relatively large parasitic capacitance will be formed between the printed wire and the reference grounding plate, because the electric field formed between the printed wire arranged inside the PCB and the reference grounding plate is “squeezed” by other printed lines, and the electric field formed between the printed line arranged at the edge and the reference grounding plate is relatively divergent.Figure 4 shows the electric field distribution between the printed wire and the reference grounding plate.
Fig. 4 schematic diagram of electric field distribution between printed circuit and reference grounding plate
Obviously, for the circuit design in this case, because the reset signal line in the PCB is arranged at the edge of the PCB and already falls outside the GND plane, the reset signal line will be greatly disturbed, resulting in the reset phenomenon of the system during ESD test.
[Treatment measures] According to the above principle analysis, it is easy to get the following two treatment measures:
1. Re-route the PCB, and move the reset signal printed circuit to the left on the PCB, so that it is in the area covered by the GND plane and far away from the edge of the PCB. At the same time, in order to further reduce the parasitic capacitance between the reset signal printed circuit and the reference grounding time, you can lay GND copper foil (connected to the adjacent GND plane through a large number of vias) on the vacant place on the layer where the reset signal printed circuit is located (in this case, the 4-layer board, and the reset signal line is arranged on the surface layer), as shown in Figure 5.
Fig. 5 revised reset signal line layout PCB real diagram
2. On the disturbed reset printed circuit, connect a capacitor in parallel near the reset pin of CPU, and the value of the capacitor can be between 100 pf and 1000 pf.